A method of performing a test such as screening a plurality of IC chips formed on a semiconductor wafer before the wafer is diced has been disclosed in, for example, the method of manufacturing a semiconductor device of JP-A-5-136243.
The following description relates to such a conventional semiconductor device manufacturing method, particularly when the above screening is performed. FIG. 6 is a flowchart showing a conventional semiconductor device manufacturing process.
According to the conventional method, at step S1, a plurality of IC chips 1 are formed on a semiconductor wafer. Wires for electrically connecting the respective terminals of the IC chips to one another in parallel are formed on scribe lines on the wafer. The wires thus formed are electrically connected to the terminals of the respective IC chips.
FIG. 7 shows an exemplary IC chip 1 formed on the semiconductor wafer and wires 2 formed on scribe lines. For example, each chip 1 has a power supply wire, a GND wire, a first input signal wire and a second input signal wire. The terminals 3a, 3b, 3c, 3d of the wires are electrically connected to corresponding wires 2a, 2b, 2c, 2d formed on the scribe lines for supplying power and providing signal communication to each IC chip 1.
Returning to FIG. 6, subsequently, at step S2 the semiconductor wafer having the IC chips 1 formed thereon is prepared. At step S3, the IC chips 1 on the semiconductor wafer are inspected to determine whether the IC chips on the semiconductor wafer are non-defective or defective.
Subsequently, a screening step S5 is performed. In this step, a voltage is simultaneously applied to the respective terminals 3 of all the IC chips 1 through the wires 2 on the scribe lines. As described above, the screening is simultaneously performed on all the IC chips 1 on the semiconductor wafer.
More particularly, the screening means 100%-inspection is performed so that IC chips 1 which contain potential defects and may become defective articles in the future are determined to be non-defective through the above inspection by using various kinds of tests. These IC chips judged to be defective are removed from the IC chips 1.
Regarding the tests used to judge whether the chip is defective, a high temperature operation test at a fixed time referred to as a burn-in test, for example, may be performed on all the chips to thereby specify IC chips 1 having initial operation failure.
Then, in a dicing step, the semiconductor wafer is cut out (diced) into a plurality of parts corresponding to the respective IC chips. IC chips which are determined to be defective in the characteristic inspection step S3 or the screening step S5 are removed. Thereafter, the remaining IC chips are subjected to a packaging step, etc. and finally semiconductor devices are completed.
As described above, all the IC chips 1 on the semiconductor wafer are electrically connected to one another in parallel. Therefore, when a short mode fault such as short-circuit between an internal power source wire and an internal GND wire occurs in some IC chips 1, excessive current flows into the IC chips 1 under the fault state in the screening step, and thus it is impossible to apply a desired voltage to other non-defective IC chips 1. Accordingly, it has been difficult in the conventional method to perform screening on all the IC chips together.
Such a problem as described above occurs not only in the screening step, but also in a conduction test in which voltages are applied to the plurality of IC chips 1 on the wafer to check the operation of the IC chips 1. Furthermore, such a problem is an even greater concern in tests, such as screening, under which the number of targets to be simultaneously tested is larger.